TSMC FINFLEX, N2 process innovations debut at 2022 North American Technology Symposium

TSMC showcased the newest innovations in its advanced logic, specialty, and 3D IC technologies at the company’s 2022 North America Technology Symposium, with the next-generation leading-edge N2 process powered by nanosheet transistors and the unique FINFLEX technology for the N3 and N3E processes making their debut.

Resuming as an in-person event after being held online in the past two years, the North America symposium in Santa Clara, California, kicks off a series of Technology Symposiums around the world in the coming months. The Symposiums also feature an Innovation Zone that spotlights the achievements of TSMC’s emerging start-up customers.

“We are living in a rapidly changing, supercharged, digital world where demand for computational power and energy efficiency is growing faster than ever before, creating unprecedented opportunities and challenges for the semiconductor industry,” said Dr. C.C. Wei, CEO of TSMC. “The innovations we will showcase at our Technology Symposiums demonstrate TSMC’s technology leadership and our commitment to support our customers through this exciting period of transformation and growth.”

Major technologies highlighted at the Symposium include:

• TSMC FINFLEX for N3 and N3E - TSMC’s industry-leading N3 technology, set to enter volume production later in 2022, will feature the revolutionary TSMC FINFLEX architectural innovation offering unparalleled flexibility for designers. TSMC FINFLEX innovation offers choices of different standard cells with a 3-2 fin configuration for ultra performance, a 2-1 fin configuration for best power efficiency and transistor density, and a 2-2 fin configuration providing a balance between the two for Efficient Performance.

With TSMC FINFLEX architecture, customers can create system-on-chip designs precisely tuned for their needs with functional blocks implementing the best optimized fin configuration for the desired performance, power and area target, and integrated on the same chip.

• N2 technology - TSMC’s N2 technology represents another remarkable advancement over N3, with 10-15% speed improvement at the same power, or 25-30% power reduction at the same speed, ushering in a new era of Efficient Performance. N2 will feature nanosheet transistor architecture to deliver a full-node improvement in performance and power efficiency to enable next-generation product innovations from TSMC customers. The N2 technology platform includes a high-performance variant in addition to the mobile compute baseline version, as well as comprehensive chiplet integration solutions. N2 is scheduled to begin production in 2025.
  
  
• Expanding ultra-low power platform - Building on the success of the N12e technology announced at the 2020 Technology Symposium, TSMC is developing N6e, the next evolution in process technology tuned to provide the computing power and energy efficiency required by edge AI and IoT devices. N6e will be based on TSMC’s advanced 7nm process and is expected to have three times greater logic density than N12e. It will serve as a part of TSMC’s Ultra-Low Power platform, a comprehensive portfolio of logic, RF, analog, embedded nonvolatile memory, and power management IC solutions aimed at applications in edge AI and the Internet of Things.
  
  
• TSMC 3DFabric 3D silicon stacking solutions - TSMC is showcasing two groundbreaking customer applications of the TSMC-SoIC chip stacking solution:
  
  -- The world’s first SoIC-based CPU employing Chip-on-Wafer (CoW) technology to stack SRAM as a Level 3 cache
  -- A groundbreaking intelligence processing unit stacked on top of a deep trench capacitor die using Wafer-on-Wafer (WoW) technology.

With N7 chips already in production for both CoW and WoW, support for N5 technology is scheduled for 2023. To meet customer demand for SoIC and other TSMC 3DFabric system integration services, the world’s first fully automated 3DFabric factory is set to begin production in the second half of 2022.